Performance Analysis of Compensated CIC Filter in Efficient Computing Using Signed Digit Number System

This paper presents efficient compensated Cascaded Integrator Comb (CIC) decimation filter to improve the passband of interest using redundant signed digit arithmetic. In redundant representations, addition can be carried out in a constant time independent of the word length of the operands. Most of the research in the last decades has concentrated on reducing the delay of addition. A hybrid adder can add an unsigned number to a signed-digit number and hence their efficient performance greatly determines the quality of the final output of the concerned circuit. The proposed structure consists of compensated section cascade with CIC decimation sections, each down-sampled by a specific down-sampling factor. The number of sections depends on the decimation factor of the original comb decimator and the number of cascaded filters for different stages. The magnitude response is improved by using FIR prefilters. The coefficients of the compensator filter are presented in a signed digits (SD) form, and can be implemented using only adders and shifts. Consequently, the resulting filter is a multiplier free filter and exhibits a high attenuation in the stopband, as well as a low passband droop.